Phase change memory devices use phase changing materials, for example, materials where a phase change can be induced by an electrical energy, where a sufficient thermal heat induced by this electrical energy will result in a temperature change in the phase change materials, for example a current or voltage applied to the material to induce heating in the phase changing material. For example, the phase changing material may change between amorphous and crystalline including partially amorphous and partially crystalline, the nature of the phased state being detectable, for example by a number of order in resistance change, typically is larger than one order, and thereby forming stored information. Typical phase changing materials suitable for memory elements include those utilizing various chalcogenide elements, for example one or more elements from Column VI of the periodic table. One particularly suitable group of alloys is the GeSbTe alloys system.
Phase changing memory elements have several advantages over other types of memory including DRAM, SRAM, and Flash memory. For example, they are non-volatile and may be written to with high speed, e.g., less than about 50 nanoseconds. Since transistors are not necessary to accomplish the read and write operations, the memory cells may be formed at high density. In addition, such memory cells are compatible with CMOS logic and are low power and low cost.
One goal for producing phase changing memory cells is to reduce the power consumption by reducing the amount of drive current required to effect a phase change in the phase changing memory element. The required drive current is dictated by the resistance of the phase changing material as well as the active area of the phase changing material, which is dictated by the area to which electric contact is made to the phase changing material (phase change memory element) to deliver a phase changing current. In general, assuming a given resistance of the phase changing material, a smaller contact area produces a higher resistance and therefore a higher level of resistive heating (temperature) for a given applied writing (drive) current. Therefore a smaller electrode contact area to the phase changing material memory element will correspondingly and desirably reduce drive current and thereby power consumption.
There have been various approaches in the prior art to reduce the phase change memory cell electrode contact area (active area). In general, prior art approaches have relied on photolithographic and etching techniques to pattern and form as small a contact area as possible. These approaches are difficult to scale down in size due the limited processing windows in lithographic and etching processes at the desired sizes. Other approaches have relied on forming complicated memory cell structures that rely on complicated and therefore costly processing steps to produce various memory elements and electrode shapes.
Thus, there is a need in the semiconductor manufacturing art for an improved phase change memory element and method for forming the same to reduce an electrical contact area to the memory element thereby reducing power consumption.
It is therefore an object of the invention to provide an improved phase change memory element and method for forming the same to reduce an electrical contact area to the memory element thereby reducing power consumption, while overcoming other shortcomings and deficiencies of the prior art.